Posted by Intel , As the world’s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art — from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
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Do you want to engineer the future? The E-core CPU team is powered by some of the brightest and most innovative minds in the industry and we need more.
Intel is during an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person.
We are designing future generations of high-performance E-core CPUs using the most advanced and innovative process technologies.
If you are looking to grow and develop your skillsets while be surrounded by highly motivated and knowledge teammates, then this is the organization for you.
We are looking for highly motivated and enthusiastic students for Summer/Fall 2023.
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Early Careers at Intel
Graduate Internship SoC Design Engineer for CAD Physical – United States
Job Responsibilities:
Testing and/or developing flows using Engineering Design Automation (EDA) tools including 1 or more areas of Design Synthesis, Auto Place and Route, Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Active/Dynamic/Leakage Power Analysis, LVS, Power-Rail Integrity, Extraction, ECO, or SPICE circuit simulation
Interfacing with Design Team to create or test flows/scripts to analyze design methodologies for cell-based and/or transistor-based designs.Validating PDK technology, library files and other collaterals used for either standard cell or custom-transistor design, layout, and signoff with EDA CAD tools.
Creating flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies.
Documenting and helping with guidelines/specs.
Job Requirement:
Good interpersonal, clear communication and good teamwork skills.
A can-do attitude driven by research and thriving on challenges.
Self-motivator with strong problem-solving skills.
Experience listed below would be obtained through a combination of your schoolwork, classes., research and/or relevant previous job and/or internship experiences. This is an entry level job and will be compensated accordingly.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Pursuing Master’s/PHD degree in Electrical/Computer Engineering or related field
0-6 months experience in:
Physical Design and Verification Tools, Flows and Methods used in VLSI back-end standard cell and/or custom-transistor based designs.
Coursework completed or enrolled in VLSI design, Digital and/or Analog Integrated Circuits; Advanced Programming Techniques and/or Advanced Data Structures
Using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Synopsys, Cadence and/or Mentor Graphics in one of more of the following areas of: Synthesis, Auto Place and Route, STA, Power, ECO, SPICE circuit simulation, statistical variation analysis, noise, cross-talk, OCV and/or ERC flows
Linux environments and basic shell scripting
Programming in 1 or more scripting languages such as Python, Perl and/or Tcl
Preferred:
1+ years of experience in 1 or more of the following:
Prior Internship or fulltime experience in hardware designBackend design EDA tools Synopsys, Cadence and/or Mentor Graphics
EDA Spice Circuit Simulators such as Spectre, HSPICE or FineSim
Knowledge in standard-cell liberty format syntax or digital circuit device-level SPICE modelling
Standard formats from 1 or more of gate-level netlist, standard parasitic formats and/or SDC constraints
Cadence Design Tools: Virtuoso Schematic Editor, ADE
EDA tool Tcl API coding
Advanced programming data structures
Machine-learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement.
For more details to apply, Click here!
DCPAE Engineer (Intern) – United States
In this position you will be joining the Data Center Platform Applications Engineering (DCPAE) organization to provide customer support in developing Intel Xeon Server and Workstation platforms.
Job Description:
Expertise to define and represent issues.
Drive issue resolution across multiple development teams, groups and divisions. Centralized communication ownership across multiple geos.
This internship position has a length of 3-6 months with the possibility to extend it as per business’ needs.
Qualifications:
Candidate must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordin
Must be currently enrolled in a Bachelor of Science degree in Electrical Engineering or Computer Engineering.
Minimum 3+ months of experience or equivalent coursework in the following areas:
Microprocessor architecture.
Preferred:
Experience or equivalent coursework in one of the following areas:
Chipset architecture.
System architecture.
Board design.
Post-silicon validation.
Lab and debug skills are required, including experience working with and analyzing output from test equipment such as oscilloscopes, volt meters and power supply.
Firmware and software experience.
Annual Salary Range for jobs which could be performed in US, California: $40,000.00-$108,000.00 (Hourly Role)
Salary range dependent on a number of factors including location and experience