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Formal Verification Intern -United Kingdom
In this highly visible role, you will be at the centre of a System-on-a-chip (SoC) design verification effort collaborating with design, with a critical impact on getting high quality and bug-free functional products to millions of customers quickly.
While working on complete formal verification for single or multiple design blocks and IPs, you will collaborate with members of the team to:
Create formal micro-architecture specifications
Develop formal verification test plans
Proving properties for the design, finding design bugs, and working closely with design teams to help improve the micro-architecture
Architecting novel and innovative solutions for verifying sophisticated design micro-architectures
Developing and implementing re-usable and optimised formal models and verification code base
Knowledge of digital design logic design and/or formal verification techniques
Understanding of CPU and GPU design, pipeline architectures, memory, DMA controllers, out-of-order and speculative instruction execution hardware, bus interconnects, and cache coherence mechanisms a plus
Able to interpret hardware specifications (using temporal logic assertion-based languages such as SVA or PSL) is a plus
Knowledge of EDA formal tools and experiences in CAD tool development is a plus
Education & Experience
Currently enrolled in a Bachelor’s, Master’s or PhD Degree program in Electronic Engineering, Computer Science, Computer Engineering, Mathematics / Applied Mathematics or a related field.
This position is a full-time internship and availability for 6 months as a minimum is preferred.